Abstract




 
   

IJE TRANSACTIONS A: Basics Vol. 15, No. 4 (November 2002) 325-328   

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  AN EFFICIENT ALGORITHM FOR OUTPUT CODING IN PAL BASED CPLDS (TECHNICAL NOTE)
 
D. Kania

Institute of Electronics, Silesian Technical University
ul. Akademicka 16, 44-100 Gliwice, Poland, kdariusz@zeus.polsl.gliwice.pl
 
( Received: March 16, 2001 – Accepted: May 15, 2002 )
 
 

Abstract    One of the approaches used to partition inputs consists in modifying and limiting the input set using an external transcoder. This method is strictly related to output coding. This paper presents an optimal output coding in PAL-based programmable transcoders. The algorithm can be used to implement circuits in PAL-based CPLDs.

 

Keywords    Partitioning, Coding, Decomposition, Programmable Logic Devices

 

References   

1 Devadas, S., and Newton, R., “Exact Algorithm forOutput Encoding, State Assignment, and Four-LevelBoolean Minimization”, IEEE Transactions onComputer-Aided Design, Vol. 10, No. 1, (1991), 13-27.

2 Kania, D., “Coding Capacity of PAL-Based Logic BlocksIncluded in CPLDs and FPGAs”, IFAC Workshop onProgrammable Devices and Systems, PDS 2000, Ostrava,February 8-9, Published for the IFAC by PERGAMON,An Imprint of Elsevier Science, (2000), 164-169.

3 Malik, S., Lauter, U., Brayton, R., K., and Vincentelli, A.,S., “Symbolic Minimization of Multilevel Logic and theInput Encoding Problem”, IEEE Transactions onComputer-Aided Design, Vol. 11, No. 7, (1992), 825-843.





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