IJE TRANSACTIONS A: Basics Vol. 27, No. 10 (October 2014) 1581-1590   

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A. Mandal and R. Mishra
( Received: February 17, 2013 – Accepted: June 26, 2014 )

Abstract    Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to be a huge researched outcome for its easy realizability in on-chip design in the field of vector rotated DSP applications. In this paper we propose a pipelined CORDIC architecture for digital demodulation in high performance, low power frequency modulated CW Radar. A complex Digital Phase Locked Loop (DPLL) has been used for digital demodulation with pipelined CORDIC module as its core processing element. The FPGA implementation of CORDIC based design has been chosen because of its inherent high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. Substantial amount of resource utilization has been reduced in proposed design. For better loop performance of first order complex DPLL during demodulation, the convergence of the CORDIC architecture is also optimized. Multiplierless BOXCAR filter has been incorporated at the final stage of the design for better information recovery from narrow samples with little energy signal and easy realization. Hardware synthesized result using Cadence design tools are presented.


Keywords    FMCW Radar, CORDIC, FPGA, DSP, DPLL, Loop performance


چکیده    فرایند سیگنال رادار، زمینه تحقیقاتی جالبی برای درک فرایند سیگنال دیجیتال قابل برنامه ریزی شده با استفاده از روش طراحی VLSI می باشد. الگوریتم های فرایند سیگنال دیجیتال (DSP) یک روش طراحی انتگرالی برای اجرای سیستم های ویژه سرعت بالا با زمان واقعی مخصوصا برای رادار با وضوح بالا را دارد. در زمان های اخیر، الگوریتم CORDIC به دلیل آسان بودن درک آن در طراحی روی تراشه(on-chip) در زمینه کاربردهای DSP بردار چرخشی به نتیجه تحقیقاتی بزرگی تبدیل شده است. در این مقاله، ما معماری CORDIC خط لوله ای را برای کشف رمز دیجیتالی در رادار CW با عملکرد بالا و بسامد توان پایین پیشنهاد می کنیم. یک حلقه قفل شده فاز دیجیتالی پیچیده برای کشف رمز دیجیتالی با ماژول CORDIC خط لوله ای به عنوان جزئ فرایندی هسته ای استفاده شده است. اجرای FPGA برای طراحی بر پایه CORDIC به علت توان ذاتی بالای سیستم به دلیل معماری خط لوله ای آن انتخاب شده است، جایی که زمان تاخیر در هر مرحله خط لوله کاهش می یابد. میزان قابل توجهی از استفاده از منابع در طرح پیشنهادی کاهش می یابد. برای عملکرد بهترDPLL پیچیده درجه اول در مدت کشف رمز، همگرایی معماری CORDIC نیز بهینه شده است. فیلتر BOXCAR در مرحله نهایی طرح برای بازیافت اطلاعات از نمونه های باریک با سیگنال کم انرژی و فهم آسان ترکیب شده است. نتیجه سنتز سخت افزاری با استفاده از ابزارهای طرح Cadence ارائه شده است.



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