Abstract




 
   

IJE TRANSACTIONS C: Aspects Vol. 28, No. 3 (March 2015) 419-425   

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  LOW SETTLING TIME ALL DIGITAL DLL FOR VHF APPLICATION
 
H. Rahimpour, M. Gholami, G. Ardeshir and H. MiarNaimi
 
( Received: May 20, 2013 – Accepted: November 14, 2014 )
 
 

Abstract    Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of each delay cells. Since this novel architecture has removed phase detector, charge pump and loop filter, the proposed structure shown occupy smaller chip area and has less settling time than conventional DLLs. This method could be implemented in a real system by means a digital signal processor device. Simulation has been done for 15 delay cells and fREF is chosen 14MHz to have output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequency band. As shown with simulations, the proposed architecture has locking time approximately 286nsec which is equal to 4 clock cycles of reference clock.

 

Keywords    DLL, Delay Locked Loop, PRP Conjugate Gradient Algorithm, Optimization, Multiplier.

 

چکیده    حلقه­های قفل شده تاخیر(DLL) و حلقه­های قفل شده فاز (PLL) به طور گسترده­ای به عنوان سنتزکننده­های فرکانسی و مدارهای بازیابی کلاک و داده در سیستمهای مخابراتی مورد استفاده قرار می­گیرند. در این مقاله، یک DLL جدید مبتنی بر الگوریتم گرادیان مزدوجPRP طراحی شده است. ساختار ارائه شده، به آشکارساز فاز-فرکانس، پمپ بار و فیلتر حلقه نیاز ندارد، بنابراین می­تواند عملکرد بهتری از لحاظ جیتر و سرعت نسبت به ساختار متداول حلقه­های قفل شده تاخیر داشته باشد. در این ساختار الگوریتم گرادیان مزدوج PRP جهت بهینه کردن تاخیر هر سلول تاخیر مورد استفاده قرار گرفته است که این موضوع به قفل دقیق­تر و سریعتر نسبت به الگوریتم بهینه­سازی گرادیان منتهی می­شود. علاوه بر این، جهت استفاده از الگوریتم گرادیان مزدوج PRP به یک بخش پردازش دیجیتال نیاز است. برای نشان دادن دقت این ساختار، شبیه­سازی برای 15 سلول تاخیر با انتخاب فرکانس ورودی 14 مگاهرتز جهت دریافت فرکانس خروجی 210 مگاهرتز انجام گرفته است. فرکانس خروجی 210مگاهرتز، یکی از کانالهای موجود در باند فرکانسی VHF ایران است. همانگونه که در شبیه­سازی­ها نشان داده شده است، ساختار پیشنهادی زمان قفلی در حدود 286 نانوثانیه داشته که این معادل با 4 سیکل کلاک ورودی است.

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