IJE TRANSACTIONS C: Aspects Vol. 28, No. 3 (March 2015) 419-425   

downloaded Downloaded: 172   viewed Viewed: 2412

H. Rahimpour, M. Gholami, G. Ardeshir and H. MiarNaimi
( Received: May 20, 2013 – Accepted: November 14, 2014 )

Abstract    Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of each delay cells. Since this novel architecture has removed phase detector, charge pump and loop filter, the proposed structure shown occupy smaller chip area and has less settling time than conventional DLLs. This method could be implemented in a real system by means a digital signal processor device. Simulation has been done for 15 delay cells and fREF is chosen 14MHz to have output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequency band. As shown with simulations, the proposed architecture has locking time approximately 286nsec which is equal to 4 clock cycles of reference clock.


Keywords    DLL, Delay Locked Loop, PRP Conjugate Gradient Algorithm, Optimization, Multiplier.


چکیده    حلقه­های قفل شده تاخیر(DLL) و حلقه­های قفل شده فاز (PLL) به طور گسترده­ای به عنوان سنتزکننده­های فرکانسی و مدارهای بازیابی کلاک و داده در سیستمهای مخابراتی مورد استفاده قرار می­گیرند. در این مقاله، یک DLL جدید مبتنی بر الگوریتم گرادیان مزدوجPRP طراحی شده است. ساختار ارائه شده، به آشکارساز فاز-فرکانس، پمپ بار و فیلتر حلقه نیاز ندارد، بنابراین می­تواند عملکرد بهتری از لحاظ جیتر و سرعت نسبت به ساختار متداول حلقه­های قفل شده تاخیر داشته باشد. در این ساختار الگوریتم گرادیان مزدوج PRP جهت بهینه کردن تاخیر هر سلول تاخیر مورد استفاده قرار گرفته است که این موضوع به قفل دقیق­تر و سریعتر نسبت به الگوریتم بهینه­سازی گرادیان منتهی می­شود. علاوه بر این، جهت استفاده از الگوریتم گرادیان مزدوج PRP به یک بخش پردازش دیجیتال نیاز است. برای نشان دادن دقت این ساختار، شبیه­سازی برای 15 سلول تاخیر با انتخاب فرکانس ورودی 14 مگاهرتز جهت دریافت فرکانس خروجی 210 مگاهرتز انجام گرفته است. فرکانس خروجی 210مگاهرتز، یکی از کانالهای موجود در باند فرکانسی VHF ایران است. همانگونه که در شبیه­سازی­ها نشان داده شده است، ساختار پیشنهادی زمان قفلی در حدود 286 نانوثانیه داشته که این معادل با 4 سیکل کلاک ورودی است.



1.     Mandal, A. and Mishra, R., "Design and implementation of digital demodulator for frequency modulated CW radar (research note)", International Journal of Engineering-Transactions A: Basics,  Vol. 27, No. 10, (2014), 1581-1590.

2.     Gholami, M., Rahimpour, H., Ardeshir, G. and MiarNaimi, H., "A new fastlock, lowjitter, and alldigital frequency synthesizer for dvbt receivers", International Journal of Circuit Theory and Applications, (2013).

3.     Gholami, M., Ardeshir, G. and Ghonoodi, H., "A novel architecture for low voltage-low power dll-based frequency multipliers", IEICE Electronics Express,  Vol. 8, No. 11, (2011), 859-865.

4.     Moallem, P. and Ehsanpour, M., "A novel design of reversible multiplier circuit", International Journal of Engineering,  Vol. 26, No. 6, (2013), 577-586.

5.     Coban, A.L., Koroglu, M.H. and Ahmed, K.A., "A 2.5-3.125-gb/s quad transceiver with second-order analog dll-based cdrs", Solid-State Circuits, IEEE Journal of,  Vol. 40, No. 9, (2005), 1940-1947.

6.     Yun, W.-J., Lee, H.-W., Shin, D. and Kim, S., "A 3.57 gb/s/pin low jitter all-digital dll with dual dcc circuit for GDDR3 dram in 54-nm cmos technology", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on,  Vol. 19, No. 9, (2011), 1718-1722.

7.     Kim, N.-S., Cho, U.-R. and Byun, H.-G., "Low voltage wide range dll-based quad-phase core clock generator for high speed network sram application", in Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005, IEEE, (2005), 533-536.

8.     Gao, X., Klumperink, E.A. and Nauta, B., "Advantages of shift registers over dlls for flexible low jitter multiphase clock generation", Circuits and Systems II: Express Briefs, IEEE Transactions on,  Vol. 55, No. 3, (2008), 244-248.

9.     Oh, K.-I., Kim, L.-S., Park, K.-I., Jun, Y.-H. and Kim, K., "Low-jitter multi-phase digital dll with closest edge selection scheme for ddr memory interface", Electronics Letters,  Vol. 44, No. 19, (2008), 1121-1123.

10.   Gholami, M. and G. Ardeshir, "Dual phase detector based delay locked loop for high speed applications", International Journal of Engineering-Transactions A: Basics,  Vol. 27, No. 4, (2014), 517-522.

11.   Gholami, M., Rahimpour, H., Ardeshir, G. and MiarNaimi, H., "Digital delay locked loop-based frequency synthesiser for digital video broadcasting-terrestrial receivers", IET Circuits, Devices & Systems,  Vol. 8, No. 1, (2014), 38-46.

12.   Rahimpour, H., Gholami, M., Miar-Naimi, H. and Ardeshir, G., "All digital fast lock dll-based frequency multiplier", Analog Integrated Circuits and Signal Processing,  Vol. 78, No. 3, (2014), 819-826.

13.   Liao, F.-R. and Lu, S.-S., "A waveform-dependent phase-noise analysis for edge-combining DLL frequency multipliers", Microwave Theory and Techniques, IEEE Transactions on,  Vol. 60, No. 4, (2012), 1086-1096.

14.   Gholami, M. and Ardeshir, G., "Jitter of delay-locked loops due to pfd", (2014).

15.   Shin, D., Song, J., Chae, H. and Kim, C., "A 7 ps jitter 0.053 mm fast lock all-digital DLL with a wide range and high resolution dcc", Solid-State Circuits, IEEE Journal of, Vol. 44, No. 9, (2009), 2437-2451.

16.   Cheng, K.-H. and Lo, Y.-L., "A fast-lock wide-range delay-locked loop using frequency-range selector for multiphase clock generator", Circuits and Systems II: Express Briefs, IEEE Transactions on,  Vol. 54, No. 7, (2007), 561-565.

17.   Gholami, M., "A novel low power architecture for DLL-based frequency synthesizers", Circuits, Systems, and Signal Processing,  Vol. 32, No. 2, (2013), 781-801.

18.   Y. Moon, D.-K. Jeong, G. Ahn and . "A 0.6-2.5-gbaud cmos tracked oversampling 3x transceiver with dead-zone phase detection for robust clock/data recovery", IEEE Journal of  Solid-State Circuits,  Vol. 36, No. 1974-1983.

19.   Cauchy, A., "Méthode générale pour la resolution des systemes d’equations simultanées", Comp. Rend. Sci. Paris,  Vol. 25, No. 1847, (1847), 536-538.

20.   Akaike, H., "On a successive transformation of probability distribution and its application to the analysis of the optimum gradient method", Annals of the Institute of Statistical Mathematics,  Vol. 11, No. 1, (1959), 1-16.

21.   Forsythe, G.E., "On the asymptotic directions of thes-dimensional optimum gradient method", Numerische Mathematik,  Vol. 11, No. 1, (1968), 57-76.

22.   Dai, Y.-H. and Yuan, Y., "A nonlinear conjugate gradient method with a strong global convergence property", SIAM Journal on Optimization,  Vol. 10, No. 1, (1999), 177-182.

23.   Li, G., Tang, C. and Wei, Z., "New conjugacy condition and related new conjugate gradient methods for unconstrained optimization", Journal of Computational and Applied Mathematics,  Vol. 202, No. 2, (2007), 523-539.

24.   Wei, Z.X., Li, G.Y. and Qi, L.Q., "Global convergence of the polak-ribiere-polyak conjugate gradient method with an armijo-type inexact line search for nonconvex unconstrained optimization problems", Mathematics of Computation,  Vol. 77, No. 264, (2008), 2173-2193.

25.   Yuan, G., "Modified nonlinear conjugate gradient methods with sufficient descent property for large-scale optimization problems", Optimization Letters,  Vol. 3, No. 1, (2009), 11-21.

26.   Yu, G., Zhao, Y. and Wei, Z., "A descent nonlinear conjugate gradient method for large-scale unconstrained optimization", Applied Mathematics and Computation,  Vol. 187, No. 2, (2007), 636-643.

27.   Kavalov, D. and Kalinin, V., "Neural network surface acoustic wave rf signal processor for digital modulation recognition", Ultrasonics, Ferroelectrics, and Frequency Control, IEEE Transactions on,  Vol. 49, No. 9, (2002), 1280-1290.

28.   Chang, H.-H. and Liu, S.-I., "A wide-range and fast-locking all-digital cycle-controlled delay-locked loop", Solid-State Circuits, IEEE Journal of,  Vol. 40, No. 3, (2005), 661-670.

29.   Yang, R.-J. and Liu, S.-I., "A 40–550 MHZ harmonic-free all-digital delay-locked loop using a variable sar algorithm", Solid-State Circuits, IEEE Journal of,  Vol. 42, No. 2, (2007), 361-373.

International Journal of Engineering
E-mail: office@ije.ir
Web Site: http://www.ije.ir