Abstract    The demand of self-testing proportionally increases with memory size in System on Chip (SoC). SoC architecture normally occupies the majority of its area by memories. Due to increase in density of embedded memories, there is a need of self-testing mechanism in SoC design. Therefore, this research study focuses on this problem and introduces a smooth solution for self-testing. In the proposed memory test algorithm, the self-testing as well as self-repair mechanisms are incorporated. This scheme repairs the detected faults and is easily integrated with SoC design. Here, an attempt has been made to implement the memory built-in-self-repair (MBISR) architecture to test and repair the faults from the embedded memories. It is little, and it supports at-fast test without timing penalty during its operation. The proposed method is a better alternative in speed and low area overhead. Thus, it plays a significant role in yield improvement.

Keywords    Embedded memory, Self-testing, Memory built-in self-repair (MBISR), System on chip (SoC), Memory test algorithm, yield improvement.

چکیده    درخواست برای خودآزمونی با اندازه حافظه در سيستم بر چيپ(SoC) فزونی يافته است. معماریSoC معمولا بخش عمده سطح را با حافظه پر می کند. با توجه به افزايش چگالی حافظه های جاسازی شده، در طراحی SoC نياز به سازوکار خود آزمونی است بنابراين، اين تحقيق بر اين مساله متمرکز بوده ويک حل هموار برای خود آزمونی معرفی می کند. در الگوريتم آزمون حافظه پيشنهادی علاوه بر خود آزمونی، سازوکار بهسازی نيز شرکت دارد. اين شما خطا های پيدا شده را اصلاح کرده و به سادگی با طرح SoC يکپارچه می شود. در اينجا کوشش شده است تا از روی حافظه های جا سازی شده، معماری حافظه built-in-self-repair (MBISR) را برای آزمايش و اصلاح خطا ها پياده سازی کند. اين کار سريع و بدون جريمه زمانی طی عمليات مربوط صورت می گيرد. روش ارائه شده شيوه بهتری از نظر سرعت و با سطح کم می باشد و بنا براين نقش قابل توجهی در بهبود نتيجه دارد.

References    1.      Wu, T.-H., Chen, P.-Y., Lee, M., Lin, B.-Y., Wu, C.-W., Tien, C.-H., Lin, H.-C., Chen, H., Peng, C.-N. and Wang, M.-J., "A memory yield improvement scheme combining built-in self-repair and error correction codes", in Test Conference (ITC), IEEE International,. (2012), 1-9. 2.      Ahmed, M.A., Rani, D.E. and Sattar, S.A., "Fpga based high speed memory bist controller for embedded applications", Indian Journal of Science and Technology,  Vol. 8, No. 33, (2015). 3.      Aljumah, A. and Ahmed, M.A., "Amba based advanced dma controller for soc", International Journal of Advanced Computer Science and Applications,  Vol. 7, No. 3, (2016), 188-193. 4.      Park, S., Lee, K., Im, C., Kwak, N., Kim, K. and Choi, Y., "Designing built-in self-test circuits for embedded memories test", in ASICs,. AP-ASIC. Proceedings of the Second IEEE Asia Pacific Conference on, (2000), 315-318. 5.      Boutobza, S., Nicolaidis, M., Lamara, K.M. and Costa, A., "A                 transparent based programmable memory bist", in Test Symposium,. ETS'06. Eleventh IEEE European, (2006), 89-96. 6.      Schanstra, I., Lukita, D., Van de Goor, A.J., Veelenturf, K. and van Wijnen, P.J., "Semiconductor manufacturing process monitoring using built-in self-test for embedded memories", in Test Conference, Proceedings., International, (1998), 872-881. 7.      Krishna, K.M. and Sailaja, M., "Low power memory built in self test address generator using clock controlled linear feedback shift registers", Journal of Electronic Testing,  Vol. 30, No. 1, (2014), 77-85. 8.      Acharya, G.P. and Rani, M.A., "Survey of test strategies for system-on chip and it's embedded memories", in Intelligent Computational Systems (RAICS), IEEE Recent Advances in, (2013), 199-204. 9.      Lee, M., Denq, L.-M. and Wu, C.-W., "A memory built-in self-repair scheme based on configurable spares", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,  Vol. 30, No. 6, (2011), 919-929. 10.    Su, C.-L., Huang, R.-F., Wu, C.-W., Luo, K.-L. and Wu, W.-C., "A built-in self-diagnosis and repair design with fail pattern identification for memories", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  Vol. 19, No. 12, (2011), 2184-2194. 11.    Lin, B.-Y., Chiang, W.-T., Wu, C.-W., Lee, M., Lin, H.-C., Peng, C.-N. and Wang, M.-J., "Redundancy architectures for channel-based 3d dram yield improvement", in Test Conference (ITC), IEEE International, (2014), 1-7. 12.    Stroud, C.E., "A designer's guide to built-in self-test, Springer Science & Business Media,  Vol. 19,  (2002). 13.    Youn, D., Kim, T. and Park, S., "A microcode-based memory bist implementing modified march algorithm", in Test Symposium,. Proceedings. 10th Asian, IEEE. (2001), 391-395. 14.    Huang, S.-Y. and Kwai, D.-M., "A high-speed built-in-self-test design for drams", in VLSI Technology, Systems, and Applications,. International Symposium on, IEEE., (1999), 50-53. 15.    Tseng, T.-W., Li, J.-F. and Hou, C.-S., "A built-in method to repair soc rams in parallel", IEEE Design & Test of Computers,  Vol. 27, No. 6, (2010), 46-57. 16.    Aljumah, A. and Ahmed, M.A., "Design of high speed data transfer direct memory access controller for system on chip based embedded products", Journal of Applied Sciences,  Vol. 15, No. 3, (2015), 576-582 17.    Zivarian, H., Soleimani, M. and Mohammadi, M.D., "Field programmable gate array–based implementation of an improved algorithm for objects distance measurement (technical note)", International Journal of Engineering-Transactions A: Basics,  Vol. 30, No. 1, (2016), 57-64. 18.    Mandal, A. and Mishra, R., "Design and implementation of digital demodulator for frequency modulated cw radar", IJE Trans. A: Basics,  Vol. 27, No. 10, (2014), 1581-1590. 19.    Hou, L., Wu, W. and Zhu, J., "Mbist design and implementation of a h. 264/avc video decoder chip", in Signal Processing Systems (ICSPS), 2nd International Conference on, IEEE. Vol. 1, (2010), V1-87-V81-90.