IJE TRANSACTIONS B: Applications Vol. 31, No. 5 (May 2018) 699-704    Article in Press

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M. Asyaei
( Received: November 06, 2017 – Accepted in Revised Form: January 16, 2018 )

Abstract    In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in gates. Furthermore, the subthreshold leakage current is decreased by using the footer transistor in diode configuration and consequently, the noise immunity is increased in the proposed circuit. Simulation results of wide fan-in OR gates in 90nm CMOS technology demonstrate 48% power reduction and 1.65 noise-immunity improvement at the same delay compared to the conventional dynamic circuit for 32-bit OR gates.


Keywords    Dynamic Circuit, Keeper, Leakage Current, Noise Immunity, Wide Fan-in Gates.


چکیده    در اين مقاله، يك طرح مداري جديد براي كاهش توان مصرفي مدارهاي ديناميكي پيشنهاد مي‌شود. در مدار پيشنهادي، از يك ترانزيستور نگهدارنده از نوع NMOS براي حفظ سطح ولتاژ گره خروجي در مقابل تسهيم بار، جريان نشتي و منابع نويز استفاده شده است. با بكارگيري طرح نگهدارنده پيشنهادي، دامنه تغييرات ولتاژ گره ديناميكي كاهش داده مي‌شود تا توان مصرفي گيت‌هاي عريض كم گردد. همچنين، با استفاده از ترانزيستور پايه در حالت ديودي، جريان نشتي زيرآستانه كم مي‌شود و در نتيجه، مصونيت در برابر نويز مدار پيشنهادي افزايش مي‌يابد. نتايج شبيه‌سازيهاي گيت‌هاي OR عريض در فناوري 90 نانومتر CMOS، 48 درصد كاهش توان مصرفي و 65/1 برابر بهبود مصونيت در برابر نويز را براي گيت‌هاي OR 32 بيتي در تاخير يكسان در مقايسه با مدار ديناميكي متداول نشان مي‌دهد.


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